ACD Automated Circuit Design
[TABLE OF CONTENTS]
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VII) DESIGNING OHMEGA-PLY® RESISTORS
A) Designing Ohmega-Ply® Resistors in Intergraph, CDX Classic
by Chuck Michie of Automated Circuit Design
The following description outlines methods for creating shapes for Ohmega-Ply® resistors, and implementing them into an Intergraph, CDX Classic layout. This does not apply to Intergraph Advance Technology Designer or Veribest PCB. It is assumed here that the user is familiar with the Ohmega-Ply® geometries required to create the desired resistor values, and therefore this document will deal only with implementation in CDX Classic.
Ohmega-Ply® resistors will typically be a minimum of 10 mils wide so a 10 mil diameter pad is defined: Ex: 10 RD. Resistor shapes must be specifically defined for resistor value, resistive material used, resistor width, and layer used. All of these factors may be shown in the symbol name such as OR150/100/10L5 or OR1.2K/100/10L5, which would be 150 ohm and 1.2k ohm respectively, 100 ohm material, 10 mils wide on layer 5. Add the pads and draw the resistor pattern on the trace layer to be used for the Ohmega-Ply® resistors. If the resistor is pattern just a single line, not serpentine, the line should be made of two segments which meet in the center. This will prevent false DRC errors when connecting to the resistor pins. Select another trace layer to be used for the 2nd etch image and draw out the block with overlapping traces. Using a trace layer for the 2nd etch block will serve as a via keep-out for the resistor shape. An odd width trace, such as 2 mils wide trace, may be added on the resistor trace layer along the edge of the 2nd etch block to act as a route keep-out around the resistor pattern if needed. This odd width trace should be nulled out in the photoplot process. Add the reference designator on one of the silk-screen or assembly layers, one that is not being used if possible.
All of the thru hole shapes will have to be modified so that the pads are defined on all layers, or at least on the trace layer(s) to be used for the Ohmega-Ply® resistors. Typically the thru hole shapes have pads defined only on Top, Bottom, and 1. To connect to the resistor pins the trace layer used for the Ohmega resistors must be mapped to the shape layer on which they are defined. If the thru hole pads are not defined on that layer also, then no connection can be made to them on that layer. Defining the thru hole pads on all layers will prepare these shapes for use with Ohmega-Ply® resistors on any layer for future designs.
The PCB trace layers must be mapped to the correct shape trace layers by editing the pad attributes in the PCB file. In this example the resistor patterns were defined on the "Inner 5" layer in the shape, so the PCB trace layer 5 should be mapped to the shape trace layer 5 in the PCB file. The 2nd etch image was defined on the "Inner 15" layer in the shape, so the PCB layer 15 should be mapped to the shape trace 15. If resistors are defined for other layers, then those should be mapped out also. The resistors may then be placed, along with all other components, and connections may be made from the resistors pins to thru pins, vias, or traces on the layer where the resistors are defined.
Defining Ohmega-Ply® resistors on negative plane layers may be done by two different methods. The keyhole or thermal relief isolation and the 2nd etch block are drawn on the shape layers selected to map to the plane and 2nd etch PCB layers. The two resistor pins should have pad and thermal names which can be nulled out in the photoplot process: Ex: 10 RD Null, 10 THERM NULL. One pin should be placed at the open end of the keyhole or thermal relief isolation, and the other pin at the opposite end of the resistor area but outside of the center of the isolation. If a resistor pin is placed in the center of the isolation a logic violation will occur when the resistor is placed on a thru pin or via. Once placed, the resistor pin at the open end of the isolation may be routed to the plane with a negative route. The opposite resistor pin may be routed to the thru pin or via by one of two methods. It may be routed on the plane as a negative route if the isolation pattern opens to the resistor area at the same point as one of the thermal pad spokes of the thermal pad, with the other spokes being covered be the isolation line. The complication with this method is that multiple signals are routed on the plane, which show up as negative logic violations in the DRC checks. Also, all other thru pins and vias on that signal must have an exclude block over them to prevent thermal pads being routed which would short them to the plane. The second method requires the resistor pins to be defined on a second layer so that a trace may be routed to the thru pin or via. This layer will not be used in the photoplot process, it is only used to eliminate the rat and indicate that the connection has been made. To complete the connection on the artwork the thru pin or via anti pad must be voided out so that copper is not removed between the hole and the resistor area. A drafting layer pad, placed over the anti pad, may be processed as a positive/negative merge in the artwork to void the anti pad. This pad may be defined on a drafting layer in the shape as overlapping circles from the center of the isolation area, and must be large enough to cover the thru pin or via anti pad. This method achieves full connectivity without the DRC errors, or the potential for plane shorts, of the first method. When photoplot files are created for the negative planes, both traces and pads must be turned on and all thru hole and via pads nulled out, leaving all anti and thermal pads.
Using these methods to design Ohmega-Ply® resistors requires some work to define the shapes, but from there it is quite simple to incorporate the resistors into a PCB layout on positive routing layers. Negative plane resistors require a bit more work, and are best suited for applications which have a large number of pull-up or pull-down resistors. These methods do achieve full logic and design rule checking, and all resistors are controlled at the schematic and/or netlist level.
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